The field of invention is data conversion, more particularly, this invention relates to low-power digital-to-analog signal converters.
Modern CMOS integrated circuit technologies facilitate the cost-effective implementation of high-density digital circuits. Digital signal processing (DSP) is thus an attractive way to process signals, including audio signals. When using DSP the achievable performance is limited exclusively by the analog-to-digital (A/D) and digital-to-analog (D/A) converters employed. Products such as compact-disc (CD), mini-disc, and digital-audio-tape (DAT) playback units require low-cost highly-linear D/A converters for their mass production.
A particularly simple D/A converter system [50] is shown in FIG. 1. In IEEE Journal of Solid-State Circuits, SC-10, December, 1975, Suarez et al. described a successive-approximation A/D converter employing internally a similar D/A converter for feedback. The operation is best described considering also the timing diagram shown in FIG. 2. Each conversion cycle consists of a reset period; a D/A conversion period; and a read-out period wherein the generated analog signal y(n) is provided to the output stage [52]. The D/A converter""s core [54] consists of a reference voltage source [56]; two nominally identical capacitors [58][60]; and a handful of switches. The D/A converter core [54] generates a voltage signal stored on the capacitors [58][60] at the end of the D/A conversion period. During the reset period, the capacitors [58][60] are discharged by two switches [62][64]. The digital word to be converted, x(n), is of N-bit resolution, where N=16. The individual bits are denoted x(n, 1), x(n, 2), . . . , x(n, N), where x(n, 1) is the least significant bit and x(n, N) is the most significant bit of x(n). The D/A conversion period consists of N sub-periods; one for each bit x(n, k), where k=1, 2, . . . , N. The DAC system [50] is synchronized by a master clock signal KM. When KM is logically xe2x80x9chigh,xe2x80x9d the driving capacitor [58] is either discharged or charged to Vref according to the value of the corresponding bit signal x(n, k). The bit signals x(n, k) are used sequentially, starting with the least significant bit x(n, 1). A switch [66] is closed in a non-overlapping period KS when KM is logically xe2x80x9clow,xe2x80x9d whereby the isolated charge portions will distribute among the two capacitors [58][60] according to the ratio of their capacitances: CA and CB.
Define v(n, k) as the voltage across the capacitors [58][60] in the kth sub-period when the switch [66] is closed. FIG. 3 shows a set of equations characterizing the operation of the D/A converter core [54]. The input digital word, x(n), is encoded as an unsigned binary-weighted number in the range from 0 to 1. The bit signals x(n, k) each attain only the values 0 and 1. The superposition principle explains that v(n, k) will be a fraction, CA/(CA+CB), of the voltage, Vrefxc2x7x(n, k), on the driving capacitor [58] plus a fraction, CB/(CA+CB), of the voltage, v(n, kxe2x88x921), on the storing capacitor [60] evaluated immediately before the switch [66] is closed. The reset operation assures that v(n, 0)=0. Recursive use of the redundant expression for v(n, k) leads to the conclusion that the generated voltage signal, y(n)=v(n, 16), ideally will attain the value y(n)=Vrefxc2x7x(n), provided that CA=CB.
In the read-out period, when the control signal KO is logically xe2x80x9chigh,xe2x80x9d the capacitors [58][60] are connected in parallel with the output stage""s [52] feedback capacitor [68]. The operational amplifier [70] (opamp) drives directly the load (not shown), i.e., the output signal Vout(t) is evaluated as a continuous-time signal. Notice that Vout(t) is a low-pass filtered representation of y(n). The low complexity and low power consumption of this D/A converter system [50] makes it very suitable for use in portable audio equipment. However, the human ear is a very delicate sensor capable of detecting even very small errors. Distortion and spurious tones more powerful than xe2x88x92100 dB relative to full scale is not acceptable. The capacitors [58][60] must match very well to achieve this level of spectral purity. Sufficiently good matching can generally not be obtained using a standard CMOS integrated-circuit technology. Post-production calibration can be used to improve the capacitor matching, but it will significantly increase the production costs and re-calibration may be necessary after a period of operation. The reference voltage source [56] is another possible source of deleterious errors. If the voltage source""s [56] output impedance is finite, the multiplicative reference voltage Vref will be modulated by the charge signal it provides. This effect may cause errors that are easily detectable by the human ear, unless the voltage source [56] is well regulated. Unfortunately, the implementation of an efficient regulation of the voltage source [56] will increase the overall power consumption considerably.
A digital-to-analog converter comprising a reference voltage source; a symmetrical network of switches and capacitors; and a digital state machine to control the switches. The general symmetry and the signal-independent load of the reference voltage source suppresses efficiently errors due to charge injection, clock feed-through, and reference-voltage modulation. The digital state machine controls the switches such as to suppress deleterious errors due to mismatch of the capacitors.
Accordingly, several objects and advantages of this invention are:
to provide low-cost digital-to-analog (D/A) converters suitable for use in portable audio applications;
to provide general-purpose, low-power, highly-linear D/A converters;
to provide linear D/A converters not relying on accurate matching of electrical parameters;
to provide mismatch-shaping D/A converters needing only a minimum of oversampling;
to provide D/A converters utilizing passive analog-domain interpolation, thus increasing the signal bandwidth without increasing the power consumption;
to provide D/A converters systems requiring only one operational amplifier.
Further objects and advantages will become apparent from a consideration of the ensuing description, the drawings, and the claims.
FIG. 1: shows a simple charge-sharing digital-to-analog converter (PRIOR ART).
FIG. 2: shows a timing diagram for the D/A converter [50] (PRIOR ART).
FIG. 3: shows a set of equations representing the ideal operation of the D/A converter [50].
FIG. 4: shows a differential charge-sharing D/A converter with time-invariant load of the reference voltage source [114].
FIG. 5: shows a timing diagram for the clock phases KMa and KMb.
FIG. 6: shows a fully-symmetrical version of the D/A converter [100].
FIG. 7: shows a timing diagram for the D/A converter [150].
FIG. 8: shows a set of equations representing the D/A converter [150].
FIG. 9: shows a set of compact equations representing the D/A converter [150].
FIG. 10: shows the full D/A converters system, including the preceding interpolation filter.
FIG. 11: shows the D/A converter [100] with a modified output stage [252].
FIG. 12: shows a set of equations modeling the output stage""s [252] behavior.
FIG. 13: shows a digital state machine used to generate the control signals KAh, KA1, KBh, KB1.
FIG. 14: shows a timing diagram for the D/A converter [150] driven by the state machine [300].
FIG. 15: shows a D/A converter system employing analog-domain interpolation.
FIG. 16: shows a set of equations modeling the behavior of the DAC system [350].
FIG. 17: shows the core D/A converter circuit used in the DAC system [350].
FIG. 18: shows the impulse responses for three sets of parameters for the DAC system [350].
FIG. 19: shows an error estimator calculating e(n) from x(n) and t(n, k).
FIG. 20: shows a switching selector generating t(n, k) such that e(n) will be approximately w(n).
FIG. 21: shows the selector-signal generator for a mismatch-shaping D/A converter [150].
FIG. 22: shows an implementation of the error estimator [452].
FIG. 23: shows a truth table for the first masking signal m1 (k).
FIG. 24: shows a truth table for the second masking signal m2(k).
FIG. 25: shows the switching selector [456].
FIG. 26: shows rough estimates of the basis signals b(n, k).
FIG. 27: shows how to choose the three signals, t(n, 16), t(n, 15), and s(n).
FIG. 28: shows the digital-logic network [480] employed in the switching selector [456].
FIG. 29: shows an implementation of the selector-signal generator [450].